1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a sense amplifier circuit provided within a semiconductor memory device.
2. Description of the Related Arts
In recent years, semiconductor memory devices exemplified by DRAMs (dynamic random access memories) have been developed on the basis of the use of leading-edge semiconductor device manufacturing processes and the scaledown of semiconductor memory devices is being carried out. In semiconductor memory devices, the size of a memory cell region is changing in the direction of shrinkage due to the ongoing scaledown in fabrication processes of the semiconductor devices. However, the scaledown as viewed form the standpoint of the whole semiconductor memory device has not been going on compared to the scaledown in the memory cell region and, for this reason, the shrinkage of the size of circuits provided in what is called a peripheral region in a semiconductor memory device has posed a new problem. This problem is remarkable particularly in sense amplifiers. In pushing forward with the scaledown of semiconductor memory devices also in the future, it is necessary to make contrivance in order to reduce a relative increase in the size of a sense amplifier on a semiconductor chip.
In order to explain a sense amplifier provided within a semiconductor memory device, a description will be given of a semiconductor memory device of a related art provided with a sense amplifier. FIG. 1 shows the configuration of a semiconductor memory device of a related art configured as a DRAM.
This semiconductor memory device is provided with m word lines 108-1 to 108-m, n sets of bit line pairs, word driver 101 that drives the word lines, data driver 102 that drives bit lines, memory cell array 103, and sense amplifier circuit 110. Each of the n bit line pairs includes bit lines 106-1 to 106-n as first bit lines and bit lines 107-1 to 107-n as second bit lines. Sense amplifier circuit 110 is provided with n sense amplifier portions 110-1 to 110-n. The sense amplifier portion is provided for each bit line pair. Here, m and n are even numbers of not less than 2. With sense amplifier portion 110-1 serving as the first one and sense amplifier portion 111-n as the n-th one, n sense amplifier portions 110-1 to 110-n are arranged in a line from left to right in the figure in this order. As will be described later, n sense amplifier portions 110-1 to 110-n share a gate electrode and a bit line potential supply line and, therefore, these sense amplifier portions are arranged as one group to form sense amplifier circuit 110.
Memory cell array 103 is such that memory cells are provided in matrix form, and contains (m×n) memory cells 104 that are arranged in m rows and n columns.
This semiconductor memory is connected to an unillustrated CPU (central processing unit) and stores data required by the CPU. And in the semiconductor memory device, during a memory access operation, word driver 101 decodes address signal ADDR as a row address from the CPU and drives word line 108-i (i=1, 2, . . . , m) selected from word lines 108-1 to 108-m according to address signal ADDR. When the word lines are driven by word driver 101, n sense amplifier portions 110-1 to 110-n supply a bit line reference potential to n bit line pairs (bit lines 106-1 to 106-n and bit lines 107-1 to 107-n) and amplify the potential of the bit lines up to the bit line reference potential. The memory access operation includes the data writing operation to the memory cells and the data reading operation from the memory cells.
During a memory access operation, data driver 102 receives address signal ADDC as a column address from the CPU. Data driver 102 decodes the address signal ADDC, and drives the j-th (j=1, 2, . . . , n) column selection line corresponding to address signal ADDC among n column selection lines. By the driving of the j-th column selection line, there are selected sense amplifier portion 110-j that is selected from n sense amplifier portions 110-1 to 110-n and the bit line pair (bit line 106-j, bit line 107-j) that is selected from n bit line pairs (bit lines 106-1 to 106-n, bit lines 107-1 to 107-n). Selected sense amplifier portion 110-j performs memory access to memory cell 104 connected to selected word line 108-i and a selected bit line pair (bit line 106-j or bit line 107-j).
FIG. 2 shows the configuration of sense amplifier circuit 110 including n sense amplifier portions 110-1 to 110-n. All of sense amplifier portions 110-1 to 110-n are of the same electrical configuration, and are provided with transistor BLEQ Tr100, gate electrode 121, and bit line potential supply line 122. Transistor BLEQ Tr100 includes transistors Tr101, Tr102 and Tr103. Gate electrode 121 is formed to be common to n sense amplifier portions 110-1 to 110-n, that is, gate electrode 121 of n sense amplifier portions 110-1 to 110-n is formed as one piece. Similarly, bit line potential supply line 122 is also provided to be common to n sense amplifier portions 110-1 to 110-n. 
Transistors Tr101 of sense amplifier portions 110-1 to 110-n connect bit lines 106-1 to 106-n, respectively, to line potential supply line 122. Transistors Tr102 of sense amplifier portions 110-1 to 110-n connect bit lines 107-1 to 107-n, respectively, to bit line potential supply line 122. Transistors Tr103 of sense amplifier portions 110-1 to 110-n are inserted between bit lines 106-1 to 106-n and bit lines 107-1 to 107-n, respectively. The gates of transistors Tr101, Tr102, Tr103 of sense amplifier portions 110-1 to 110-n are commonly connected to gate electrode 121. Gate electrode 121 and bit line potential supply line 122 extend in a row direction with respect to memory cell array 103, and sense amplifier portions 110-1 to 110-n are connected in a row direction with respect to memory cell array 103 from the first one to the last one from left to right in the figure in this order. Bit line potential VBLP is supplied to bit line potential supply line 122 as the above-described bit line reference potential.
The timing chart of FIG. 3 shows the relationship between a signal supplied to a word line and precharge signal BLEQsig. When a word line, i.e., selected word line 108-i is not driven by word driver 101, precharge signal BLEQsig is supplied to gate electrode 121. That is, the signal level of precharge signal BLEQsig is in an active state. At this time, transistors Tr101 of sense amplifier portions 110-1 to 110-n are each in an ON-state and supply bit line potential VBLP to bit lines 106-1 to 106-n, transistors Tr102 are each in an ON-state and supply bit line potential VBLP to bit lines 107-1 to 107-n, and transistors Tr103 are each in an ON-state and equalize the potentials of bit lines 106-1 to 106-n and of bit lines 1076-1 to 107-n. 
When a word line is driven by word driver 101 during a memory access operation, precharge signal BLEQsig is not supplied to gate electrode 121. That is, as shown in FIG. 3, the signal level of precharge signal BLEQsig changes from an active state to an inactive state, and immediately thereafter the word line is brought into an active state.
When the memory access operation is finished, the word line comes to a nondriven state and precharge signal BLEQsig is supplied to gate electrode 121. That is, as shown in FIG. 3, the signal level of precharge signal BLEQsig changes from an inactive state to an active state.
FIG. 4 shows the plan configuration of sense amplifier circuit 110 having n sense amplifier portions 110-1 to 110-n. In FIG. 4, however, the descriptions of an interlayer insulating film and an upper-level interconnect layer are omitted. In the figure, the portions hatched with thin oblique solid lines indicate gate electrodes 121, and the portions hatched with thick oblique solid lines indicate contacts 141 to 143 used for the connection with bit lines.
Gate electrode 121 is provided in the shape of the letter T for each of sense amplifier portions 110-1 to 110-n. For each of sense amplifier portions 110-1 to 110-n, gate electrode 121 contains row-direction gate electrode portion 121a that extends in the row direction, i.e., in the horizontal direction of the figure and column-direction gate electrode portion 121b that is connected perpendicularly to row-direction gate electrode portion 121a. 
Each of sense amplifier portions 110-1 to 110-n is further provided with first bit line-connected active region 131, second bit line-connected active region 132, contact region 133, first bit line contact 141, second bit line contact 142, and bit line potential supply contact 143. For each of sense amplifier portions 110-1 to 110-n, first bit line contact 141 is formed on first bit line-connected active region 131 and connected to a relevant one among bit lines 106-1 to 106-n, second bit line contact 142 is formed on second bit line-connected active region 132 and connected to a corresponding one among bit lines 107-1 to 107-n, and bit line potential supply contact 143 is provided in contact region 133 and connected to bit line potential supply line 122.
For each of sense amplifier portions 110-1 to 110-n, transistor Tr101 is provided between first bit line-connected active region 131 and contact region 133, and the gate of transistor Tr101 is connected to row-direction gate electrode portion 121a. Similarly, transistor Tr102 is provided between second bit line-connected active region 132 and contact region 133, and the gate of transistor Tr102 is connected to row-direction gate electrode portion 121a. Also, transistor TR103 is provided between first bit line-connected active region 131 and second bit line-connected active region 132 and the gate of transistor TR103 is connected to column-direction gate electrode portion 121b. Concretely, transistors Tr101, Tr102 are arranged in such a manner that the channel regions thereof are positioned on the underside of row-direction gate electrode portion 121a via a gate insulating film. Transistor Tr103 is arranged in such a manner that the channel region thereof is positioned on the underside of column-direction gate electrode portion 121b via a gate insulating film.
Sense amplifier circuit 110 contains n/2 pieces of contact regions 133, and each of contact regions 133 is shared by odd-number-th sense amplifier portions 110-1, 110-3, . . . , 110-(n−1) and even-number-th sense amplifier portions 110-2, 110-4, . . . , 110-n adjacent to the odd-number-th sense amplifier portions on the right side thereof in the figure. That is, h-th contact regions (h=1, 2, . . . , n/2) are shared by (2h−1)-th sense amplifier portion and 2h-th sense amplifier portion.
Now consideration is given to the size of an odd-number-th sense amplifier portion and an even-number-th sense amplifier portion that shares contact region 13 along with this odd-number-th sense amplifier portion. Because all of the odd-number-th sense amplifiers have the same shape and all of the even-number sense amplifier portions have the same shape, sense amplifier portions 110-1, 110-2 will be considered here.
The length of sense amplifier portions 110-1, 110-2 in the row direction, i.e., the horizontal direction in the figure is denoted by X100. Length X100 is a sum of row-direction length X101 of sense amplifier portion 110-1, row-direction length X102 of sense amplifier portion 110-2, and row-direction length X103 of bit line potential supply contact 143. Here, it is assumed that length X101 and length X102 are equal.
Sense amplifier portion 110-1 and sense amplifier portion 110-2 have the same column-direction length and this length is denoted by Y100. As shown in FIG. 4, length Y100 is a sum of length Y101, length Y102, length Y103 and length Y104. In first bit line-connected active region 131 and second bit line-connected active region 132, length Y101 indicates a column-direction length of a region in which first bit line contact 141 and second bit line contact 142 are each arranged. Length Y102 indicates a column-direction length of a region in which first bit line-connected active region 131 and second bit line-connected active region 132 overlap column-direction gate electrode portion 121b. Length Y102 is a sum of column-direction length Y102-1 of a part of column-direction gate electrode portion 121b to which the gate of transistor Tr103 is connected and column-direction of length Y102-2 of a part which is other than the portion corresponding to length Y102-1. Length Y103 indicates the width of row-direction gate electrode portion 121a. Length Y104 indicates the column-direction length of contact region 133.
In the semiconductor memory device of a related art shown in FIGS. 1, 2 and 4, for example, there occurs the problem that it is impossible to reduce the column-direction size of sense amplifier circuit 110 for the following reason.
First, transistor Tr103 is arranged in column-direction gate electrode portion 121b. For this reason, above-described lengths Y102-1, Y102-2 become necessary. Thus, transistor Tr103 is arranged in column-direction gate electrode portion 121b, and hence above-described length Y101 becomes necessary because first bit line contact 141 and second bit line contact 142 are respectively arranged in first bit line-connected active region 131 and second bit line-connected active region 132 by just that much. Furthermore, above-described length Y104 becomes necessary because bit line potential supply contact 143 is arranged in contact region 133.
Therefore, in order to reduce the size of a sense amplifier circuit, it is necessary to reduce the size of transistor Tr103.
Examples of known techniques for reducing the area of memory cells and sense amplifiers on a chip in a semiconductor memory device and techniques for improving the characteristics of sense amplifiers are as follows.
JP-A-2000-022108 discloses a semiconductor memory device that permits a reduction of the total parasitic capacitance of input and output lines and a reduction of the area of sense amplifier drivers on a semiconductor chip. This semiconductor memory device is provided with a memory cell array region, a sense amplifier region and a subword driver region and a cross region of the sense amplifier region and the subword driver region. The sense amplifier region and the subword driver regions are arranged adjacent the memory cell region. A switch MOS transistor between an main input/output line and a local input/output line is arranged in the above-described cross region, a folded gate MOS transistor is used in this switch MOS transistor, an inner diffusion layer to a folded gate is connected to the main/output line whereas an outer diffusion layer is connected to the local input/output line, whereby it is possible to reduce the total parasitic capacitance of the input/output lines and it is possible to reduce the area of sense amplifiers.
US 2003/0173593A1 discloses a semiconductor memory device capable of high-speed reading and of reducing the area of memory cells. This semiconductor memory device is provided with a plurality of folded bit line pairs arranged parallel to each other, a plurality of word lines orthogonal to the plurality of bit line pairs, and dynamic memory cells that are arranged in matrix shape in positions corresponding to points of intersection of the multiple bit line pairs and the multiple word lines. Each dynamic memory cell is provided with one transistor and one capacitor. In this semiconductor memory device, one electrode of a capacitor of each memory cell, together with one electrode of each of other multiple capacitors arranged in matrix shape, is connected to a common electrode, the other electrode of the capacitor is connected to a source electrode of a transistor, a drain electrode of the transistor is connected to a bit line pair, and a gate electrode of the transistor is connected to a word line. If half of the pitch of word lines is denoted by F, the pitch of the bit lines of a bit line pair is larger than 2F and smaller than 4F.
US 2005/0270819A1 discloses a semiconductor memory device that has a sense amplifier constituted by a pair transistor and enables the sense amplifier area to be reduced without a deterioration in the characteristics of the pair transistor. In this semiconductor memory device, a pair transistor having a prescribed function is arrayed by being repeated a plurality of times. Transistors adjacent to each other in the row direction are regarded as a pair transistor and this pair transistor is provided in quantities of multiple sets. Transistors whose arrangement relation is an oblique direction are regarded as a pair transistor and this pair transistor is further provided in quantities of multiple sets. These pair transistors are arrayed in multiple pairs, whereby the pair transistor groups are formed so that the sense amplifier area can be reduced.
US 2004/0026759 discloses a semiconductor device in which a DRAM region and a high-speed CMOC logic region are arranged in a mixed manner, and the sensitivity of sense amplifiers is increased in this semiconductor device. In this semiconductor device, a gate electrode pair of an N-type sense amplifier transistor and a gate electrode pair of a P-type sense amplifier transistor that constitute a CMOS sense amplifier of a DRAM are each arranged parallel within one active region in the same direction as bit lines, and an adjacent N-type sense amplifier transistor pair and an adjacent P-type sense amplifier transistor pair are isolated and separated by an element isolating region.
U.S. Pat. No. 5,389,810 discloses a semiconductor device whose layout size can be shrunk when it is applied to a sense amplifier. This semiconductor device is provided with a semiconductor layer having a top surface, an active region formed on the top surface of the semiconductor layer, an isolation region that is formed on the top surface of the semiconductor layer and encloses the active region, and a pair of MOSFETs formed in the active region. The pair of MOSFETs has a structure that is symmetrical with respect to a first symmetric plane substantially perpendicular to the top surface of the semiconductor layer and also symmetrical with respect to a second symmetric plane perpendicular to both the top surface of the semiconductor layer and the first symmetric plane. Each of the MOSFETs has a source region, a drain region and a channel region that are formed on a surface of the active region. The source region is formed to be common to the pair of MOSFETs, and each of the drain regions is separated from the source region by each of the channel regions.
As described above, some techniques capable of reducing the size of a sense amplifier circuit on a chip have been proposed. However, these techniques have the problems that the interconnect layout on a chip becomes complicated and that there is room for a further shrinkage of area.